1. Field of the Invention
The present application relates to a Static Random Access Memory (SRAM), and particularly relates to a SRAM with data controlled power supply.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional SRAM. The SRAM comprises a SRAM cell 10 and a sense amplifier (not shown). The conventional SRAM cell 10 comprises six switch devices, i.e., a so-called 6T SRAM cell. The switch devices Me and Mf are the access switch devices, and also called pass switch devices. The latch circuit 11 comprises two inverters 11a and 11b, and each one of the inverters 11a and 11b comprises two switch devices. When a logic value (i.e., the bit value stored) in the SRAM cell 10 is read, the voltage level of the first bit-line 12 and the second bit-line 16 are charged to a high voltage level. Then, the voltage level of the word-line 14 is raised to a high voltage level to turn on the access switch devices Me and Mf. Depending on the data stored in the SRAM cell, one of the storage nodes (either Na or Nb) will be at logic “Low” voltage level, and the corresponding bit-line (either the first bit-line 12, or the second bit-line 16) will be pulled down.
The sense amplifier of the SRAM then determines the logic value stored in the latch circuit 11 according to the voltage levels of the first bit-line 12 and the second bit-line 16. In addition, when a logic value (i.e., the bit value being written) is written to the SRAM cell 10, the voltage level of the word-line 14 is charged to a high voltage level to turn on the access switch devices Me and Mf. Then, if the bit value being written is logic 1, the voltage level of the first bit-line 12 is charged to the high voltage level and the voltage level of the second bit-line 16 is discharged to the low voltage level; or if the bit value being written is logic 0, the voltage level of the first bit-line 12 is discharged to the low voltage level and the voltage level of the second bit-line 16 is charged to the high voltage level.
Accordingly, the logic value (i.e., the bit value being written) is written into the latch circuit 11 by complementing the voltage levels of the first bit-line 12 and the second bit-line 16.
When the bit value of logic 0 is read from the latch circuit 11, the latch circuit 11 discharges the voltage level of the bit-line coupled to the logic 0 storage node of the latch circuit 11. However, the electric charge on the bit-line is also poured to the cell storage node (Na or Nb) coupled to the bit-line when the bit value of logic 0 is read from the latch circuit 11. Furthermore, since the access switch device (Me or Mf), or called pass switch device, forms a voltage divider with the pull-down switch device of the inverter in the latch circuit 11, the cell storage node (Na or Nb) of the latch circuit may suffer from a disturb voltage, which is called the Read-Select-Disturb phenomenon. If the disturb voltage level is large enough to flip the opposite side inverter of the latch circuit 11, the logic value stored in the latch circuit 11 could be flipped, and the sense amplifier may read a wrong value from the latch circuit 11.
Furthermore, in the process of reading or writing the bit value into the latch circuit 11, when the voltage level of the word-line 14 is charged to the high voltage level, all of the access switch devices Me or Mf in the SRAM cells coupled to the word-line 14 are turned on, then the SRAM cells that are coupled to the word-line 14 but not coupled to the bit-lines 12 and 16 may also suffer from a disturb phenomenon similar to the Read-Select-Disturb phenomenon. Thus, the logic values stored in the aforementioned SRAM cells could be changed, which is called the Half-Select-Disturb phenomenon. The Half-Select-Disturb phenomenon is called Read-Half-Select-Disturb when the Half-Select-Disturb phenomenon occurs in the process of reading. Otherwise, the Half-Select-Disturb phenomenon is called Write-Half-Select-Disturb as the Half-Select-Disturb phenomenon occurs in the process of writing.
Since the access switch devices (e.g., the switch devices Me and Mf in FIG. 1) have both the role of passing the write-in data into the latch circuit 11 and passing the read-out data to the bit-lines, the read stability of the data and the data write-in speed of the SRAM is a trade-off. To reduce Read-Select-Disturb and Half-Select-Disturb, the access switch devices need to be sized down. On the other hand, to improve Write Margin (WM) and write-in speed, the access switch devices need to be sized up. In addition, the supply voltage level of the SRAM is getting lower in advanced manufacturing processes, and therefore the threshold voltage (VT) of the switch device in the SRAM is lower also, while the spread of VT (called VT scatter) becomes larger. Accordingly, the stability of the data stored in the latch circuit 11 is more easily affected by the spread or variation of the threshold voltage (VT) of the switch device in the SRAM. Therefore, providing a stable and high speed SRAM cell is a significant concern in this field.